As shown in FIG. 1, a typical computer system (10) has, among other components, a microprocessor (12), one or more forms of memory (14), integrated circuits (16) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (19), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (10).
In order to properly accomplish such tasks, the computer system (10) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (18) generates a system clock signal (referred to and known in the art as xe2x80x9creference clockxe2x80x9d and shown in FIG. 1 as SYS_CLK) to various parts of the computer system (10). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor (12) and the other components of the computer system (10) use a proper and accurate reference of time.
One component used within the computer system (10) to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., xe2x80x9cchip clock,xe2x80x9d is a type of clock generator known as a phase locked loop, or xe2x80x9cPLLxe2x80x9d (20). The PLL (20) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a system signal. Referring to FIG. 1, the PLL (20) has as its input the system clock, which is its reference signal, and outputs a chip clock signal (shown in FIG. 1 as CHIP_CLK) to the microprocessor (12). The system clock and chip clock have a specific phase and frequency relationship controlled by the PLL (20). This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor (12) use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL (20), however, the operations within the computer system (10) become non-deterministic.
FIG. 2 shows a representative PLL (200). The representative PLL (200) includes a PLL core (201), buffers (212, 214), a feedback loop and a divide by N block (216). The PLL core (201) aligns the transition edge and frequency of the system clock (SYS_CLK) and a feedback loop signal (219). The PLL core (201) adjusts its output frequency in order to zero any phase and frequency difference between the system clock (SYS_CLK) and the feedback loop signal (219). The addition of the divide by N block (216) in the feedback loop enables the PLL core (201) to multiply the system clock (SYS_CLK). Multiplying the system clock is useful when the chip clock (CHIP_CLK) must have a higher frequency than the system clock (SYS_CLK). By adding the divide by N block (216), the chip clock (CHIP_CLK) frequency should be N times faster to allow the phase and frequency difference between the system clock (SYS_CLK) and the feedback loop signal (219) to zero. The representative PLL (200) may also have buffers (212, 214) to drive a larger resistive and/or capacitive load. The buffers (212, 214) are in the feedback loop so that the delay created by the buffers (212, 214) is zeroed by the PLL core (201).
The PLL core (201) adjusts the phase and frequency difference between the system clock (SYS_CLK) and the feedback loop signal (219). System clock (SYS_CLK) and the feedback loop signal (219) are used as inputs to a phase-frequency detector (202). The phase-frequency detector (202) measures whether the phase and frequency difference between the system clock and the feedback loop signal (219) are correct. An adjustment in the phase or frequency produces signals that control a charge pump (204) and a charge pump (234). The phase-frequency detector (202) indicates that the charge pumps (204, 234) should increase or decrease its output using control signals up, U (203), and down, D (205). The charge pump (204) adds or removes charge from a capacitor, C1 (206), that changes the DC value at the input of a bias-generator (208). The capacitor, C1 (206), is connected between a power supply, VDD, and an input voltage, VCRTL (207). The charge pump (204) adds or removes charge from an output, VBP (209), of a bias-generator (208).
The bias-generator (208) produces control voltages, VBP (209) and VBN (211), in response to the input voltage, VCTRL (207). The PLL core (201) may be self-biased by adding the charge pump (234) to the bias-generator (208) output, VBP (209). The addition of a second charge pump (234) allows the removal of a resistor in series with the capacitor C1 (206). A voltage-controlled oscillator (210) produces an output that has a frequency related to the control voltages, VBP (209) and VBN (211). The output (213) from the voltage-controlled oscillator, after being buffered by the buffers (212, 214), provides a frequency, N times as fast as the system clock (SYS_CLK), to other circuits. Ideally, the chip clock (CHIP_CLK) output is a constant multiple by N of the system clock (SYS_CLK) input. The chip clock (CHIP_CLK), however, is affected by power supply noise.
One common performance measure for a PLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, in a repeated output pattern, such as a clock signal, a transition that occurs from one state to another does not happen at the same time relative to other transitions. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements of an output. The system clock may have jitter that may need to be filtered by the PLL. The PLL may need to follow and compensate for jitter at the PLL output.
Phase locked loops are basically second order feedback control systems. As such, the phase locked loop can be described in the frequency domain as having a damping factor and natural frequency. The damping factor and natural frequency are fixed by the selection of the PLL circuit parameters. The loop bandwidth is defined as the PLL input frequency at which the PLL output magnitude is 3 dB lower than the PLL output magnitude when the PLL input frequency is zero (DC). The loop bandwidth determines to a large degree the speed at which the phase locked loop can react to a disturbance. The PLL should have a low loop bandwidth so that input clock jitter is filtered. Power supply noise will, however, have a certain noise-versus-frequency characteristic. The PLL loop bandwidth may need to be increased to recover from the generation of output jitter caused by power supply noise.
According to one aspect of the present invention, an integrated circuit including a clock path for carrying a clock signal; a power supply path adapted to receive power from a power supply; a phase locked loop connected to the power supply path including a voltage-controlled oscillator for generating a frequency signal dependent on an input thereto, a phase-frequency detector for detecting a phase difference between the clock signal and the frequency signal, and a bias-generator arranged to output a voltage to the input of the voltage-controlled oscillator responsive to the phase-frequency detector; and an adjustment circuit operatively connected to the input of the voltage-controlled oscillator where the adjustment circuit modifies the voltage output by the bias-generator.
According to one aspect of the present invention, a phase locked loop including a voltage-controlled oscillator for generating a frequency signal dependent on an input thereto, a phase-frequency detector for detecting a phase difference between a clock signal and the frequency signal, a bias-generator arranged to output a voltage to the input of the voltage-controlled oscillator responsive to the phase-frequency detector, and an adjustment circuit operatively connected to the input of the voltage-controlled oscillator where the adjustment circuit modifies the voltage output by the bias-generator.
According to one aspect of the present invention, a method for modifying an operating characteristic of a phase locked loop including generating a frequency signal, comparing the frequency signal to a clock signal, adjusting the generating based on the comparing using a bias-generator, generating a binary control word, adjusting an output of the bias-generator in the phase locked loop dependent on the binary control word, and operating the phase locked loop where the adjusting the output of the bias-generator modifies an operating characteristic of the phase locked loop.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.